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| PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET Rev. 01 -- 17 November 2009 Product data sheet 1. Product profile 1.1 General description SiliconMAX logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low on-state resistance Suitable for high frequency applications due to fast switching characteristics 1.3 Applications Computer motherboards DC-to-DC convertors Switched-mode power supplies 1.4 Quick reference data Table 1. VDS ID Ptot Quick reference Conditions Tsp = 80 C; VGS = 10 V; see Figure 1 Tsp = 80 C; see Figure 2 Min Typ Max 30 20 3.5 Unit V A W drain-source voltage Tj 25 C; Tj 150 C drain current total power dissipation gate-drain charge Symbol Parameter Dynamic characteristics QGD VGS = 4.5 V; ID = 20 A; VDS = 15 V; Tj = 25 C; see Figure 12 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 10 and 11 14 nC Static characteristics RDSon drain-source on-state resistance 4.4 5.5 m NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 2. Pinning information Table 2. Pin 1 2 3 4 5 6 7 8 S S S G D D D D Pinning information Symbol Description source source source gate drain drain drain drain 1 4 mbb076 Simplified outline 8 5 Graphic symbol D G S SOT96-1 (SO8) 3. Ordering information Table 3. Ordering information Package Name PSMN005-30K SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number 4. Limiting values Table 4. Symbol VDS VGS ID IDM Ptot Tstg Tj IS ISM Limiting values Parameter drain-source voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tsp = 80 C Tsp = 25 C; tp 10 s; pulsed Tsp = 80 C; VGS = 10 V; see Figure 1 Tsp = 25 C; tp 10 s; pulsed; see Figure 3 Tsp = 80 C; see Figure 2 Conditions Tj 25 C; Tj 150 C Min -20 -55 -55 Max 30 20 20 60 3.5 150 150 20 60 Unit V V A A W C C A A In accordance with the Absolute Maximum Rating System (IEC 60134). Source-drain diode PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 2 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 120 Ider (%) 80 03aa25 120 Pder (%) 80 03aa17 40 40 0 0 50 100 150 Tsp (C) 200 0 0 50 100 150 Tsp (C) 200 Fig 1. Normalized continuous drain current as a function of solder point temperature 103 ID (A) 102 RDSon = VDS / ID Fig 2. Normalized total power dissipation as a function of solder point temperature 03ah05 tp = 10 s 100 s 1 ms 10 ms 10 1 DC 100 ms 10-1 10-2 10-1 1 10 VDS (V) 102 Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 3 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 5. Thermal characteristics Table 5. Symbol Rth(j-sp) Thermal characteristics Parameter Conditions Min Typ Max 20 Unit K/W thermal resistance from junction mounted on a metal clad board; to solder point see Figure 4 102 Zth(j-sp) (K/W) 03ah04 10 = 0.5 0.2 0.1 tp T 1 0.05 0.02 P = single pulse 10-1 10-4 10-3 10-2 10-1 1 tp T t 10 tp (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 4 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 6. Characteristics Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = 25 C ID = 1 mA; VDS = VGS; Tj = 150 C; see Figure 9 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 9 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 9 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 30 V; VGS = 0 V; Tj = 25 C VDS = 30 V; VGS = 0 V; Tj = 150 C VGS = 20 V; VDS = 0 V; Tj = 25 C VGS = -20 V; VDS = 0 V; Tj = 25 C VGS = 4.5 V; ID = 13 A; Tj = 25 C; see Figure 10 and 11 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 10 and 11 Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf gfs VSD trr Qr total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time transfer conductance source-drain voltage reverse recovery time recovered charge VDS = 15 V; ID = 20 A; Tj = 25 C IS = 15 A; VGS = 0 V; Tj = 25 C; see Figure 14 IS = 10 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 25 V; Tj = 25 C VDS = 15 V; RL = 15 ; VGS = 10 V; RG(ext) = 6 ; Tj = 25 C VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 13 ID = 20 A; VDS = 15 V; VGS = 4.5 V; Tj = 25 C; see Figure 12 34 15 14 3100 605 405 18 16 65 45 60 0.81 35 20 1.3 nC nC nC pF pF pF ns ns ns ns S V ns nC Min 30 0.5 1 Typ 6.6 4.4 Max 3.4 3 1 0.5 100 100 8 5.5 Unit V V V V A mA nA nA m m Static characteristics Source-drain diode PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 5 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 60 10 V 4.5 V ID (A) 03ah06 60 VDS > ID x RDSon ID (A) 03ah08 4V 3.8 V 40 40 3.6 V 20 3.4 V 3.2 V 20 Tj = 150 C VGS = 3 V 0 0 0.2 0.4 0.6 0.8 1 VDS (V) 0 0 1 2 3 25 C 4 VGS (V) 5 Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values 03af66 102 03ah18 1 ID (A) 10-1 C (pF) 10-2 Ciss 10 Coss Crss 10-3 min typ max 10-4 10-5 10-6 1 10-1 1 10 VDS (V) 102 0 1 2 3 VGS (V) 4 Fig 7. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Fig 8. Sub-threshold drain current as a function of gate-source voltage PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 6 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 4 VGS(th) 03af65 0.02 RDSon () 0.016 03ah07 Tj = 25 C VGS = 3.8 V (V) 3 max 4V 0.012 2 typ 0.008 4.5 V 1 min 0.004 10 V 0 -60 0 20 100 Tj (C) 180 0 20 40 ID (A) 60 Fig 9. Gate-source threshold voltage as a function of junction temperature 2 a 1.5 03af18 Fig 10. Drain-source on-state resistance as a function of drain current; typical values 10 VGS (V) 8 ID = 20 A Tj = 25 C VDD = 15 V 03ah11 6 1 4 0.5 2 0 -60 0 60 120 Tj (C) 180 0 0 20 40 60 QG (nC) 80 Fig 11. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 12. Gate-source voltage as a function of gate charge; typical values PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 7 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 104 03ah10 60 VGS = 0 V IS (A) 03ah09 C (pF) Ciss 40 103 Coss Crss Tj = 150 C 102 10-1 1 10 VDS (V) 102 0 0 0.4 20 25 C 0.8 VSD (V) 1.2 Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Fig 14. Source current as a function of source-drain voltage; typical values PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 8 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 7. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 pin 1 index Lp 1 4 A1 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 o 0.010 0.057 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.041 0.228 0.016 0.024 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 15. Package outline SOT96-1 (SO8) PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 9 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 8. Revision history Table 7. Revision history Release date 20091117 Data sheet status Product data sheet Change notice Supersedes Document ID PSMN005-30K_1 PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 10 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 9. Legal information 9.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PSMN005-30K_1 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 -- 17 November 2009 11 of 12 NXP Semiconductors PSMN005-30K N-channel TrenchMOS SiliconMAX logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 November 2009 Document identifier: PSMN005-30K_1 |
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